1. Field of the Invention
Embodiments of the invention relate to a semiconductor device package and packaging technique. More particularly, embodiments of the invention relate to a semiconductor device packaging scheme adapted for use with a plurality of stacked semiconductor devices.
This application claims priority from Korean Patent Application No. 10-2005-0078863 filed on Aug. 26, 2005, the subject matter of which is herein incorporated by reference in its entirety.
2. Description of the Related Art
Semiconductor packaging technology is one of the key technologies for realizing slim, light and small electronic devices. A variety of types of semiconductor packages have evolved over time in order to realize ever increasing high density packaging, such as the dual inline package (DIP), the small outline package (SOP) and the ball grid array (BGA). A key issue with implementing high density electronics is that the area occupied by a semiconductor chip's package should be reduced when possible, which is often accomplished by reducing the width of the package's wires, the pitch of the package's external terminals and the size of the package's outer casing.
Another approach to realizing high density packaging includes the “multi-chip package”, which refers to devices where multiple semiconductor chips are incorporated into a single package body. A variant of the multi-chip package is the “stacked-type multi-chip package” which refers to devices in which multiple semiconductor devices are sequentially stacked.
Two examples of multi-chip packaging schemes are known as the system-in-package (SIP), which refers to devices that include multiple semiconductor devices performing different functions in a single package body, and the system-on-chip (SOC), which refers to devices that incorporate memory, logic devices and analog circuitry in a single package body, thereby realizing a system in one package.
Unfortunately, the system-on-chip (SOC) technology has many problems. From the viewpoint of memory chips, it can be difficult to lower the power supply voltage beyond a certain point. From the viewpoint of the logic device, noise reduction is necessary. Further, when an SOC package includes both analog circuitry implemented via bipolar processes as well as memory and logic implemented through metal oxide semiconductor (MOS) processes, manufacturing using CMOS processes becomes difficult.
In light of the above-described problems, the SIP approach is attracting a lot of attention as an alternative to the SOC because SIPs can be developed in a short time and at low cost. Unfortunately, conventional semiconductor devices have been designed with no consideration for SIP products, especially from the viewpoint of pad arrangement. For instance, when mounting SIP devices on printed circuit board (PCBs), short circuits tend to form between adjacent bonding wires connecting the SIPs to PCBs, and routing can be difficult due to high circuit complexity.
In SIP devices that use a plurality of stacked semiconductor chips and that interconnect semiconductor chips with PCBs using wire bonding, the size of each sequentially stacked semiconductor chip becomes smaller from the lowermost to the uppermost semiconductor chips. This approach is used in order to prevent an upper semiconductor chip from interfering with a lower semiconductor chip. However, in situations where an upper semiconductor chip and a lower semiconductor chip have different sizes, the distance between chip pads for the upper chip and respective PCB substrate pads can increase in comparison to the lower chip. Unfortunately, due to this increase in bonding wire lengths, the bonding wire's strength is reduced and the wire can droop under its own weight.
Semiconductor chips enclosed in an SIP generally include a memory chip and a logic chip. In the case where the memory chip and analog-logic chips are stacked, the respective bonding wires for the memory chip and analog-logic chip can become tangled because analog-logic chips tend to have more pins than memory chips. Accordingly, there is the need for a solution to realize slim, light and small SIPs as well as to be able to allow direct access testing for each semiconductor chip in an SIP in order to ensure high reliability.